When designing an integrated circuit including semiconductor devices, engineers or designers typically rely on computer design tools to help create an integrated circuit schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the integrated circuit device in or on a semiconductor substrate, the integrated circuit device schematic must be translated into a physical representation or layout, which itself can be transferred onto the surface of the semiconductor substrate. Computer-aided design (CAD) tools can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed integrated circuit device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
Software programs employed by the CAD tools to produce layout representations are typically structured to implement a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines. Typically, the formation of integrated circuit devices on a wafer relies on lithography processes. As is well known, lithography processes can be used to transfer a pattern of a photomask (also referred to as a mask or a reticle) to a wafer. For instance, patterns can be formed from a photoresist layer disposed on the wafer by passing light energy through a mask having an arrangement to image the desired pattern onto the photoresist layer.
There is a pervasive trend in the field of integrated circuit fabrication to increase the density with which various structures are arranged. For example, feature size, line width, and the separation between features and lines are becoming increasingly smaller. Yield of integrated circuit fabrication processes is affected by factors such as mask pattern fidelity, optical proximity effects and photoresist processing. Optical proximity correction (OPC) has been used to improve image fidelity. In general, current OPC techniques involve conducting computer simulations that take initial data sets having information relating the desired patterns and manipulate the data sets to arrive at corrected layouts or data sets in an attempt to compensate for the above-mentioned concerns. The photomask can then be made in accordance with the corrected layout. Briefly, the OPC process can be governed by a set of geometrical rules (e.g., “rule-based OPC” employing fixed rules for geometric manipulation of the data set), a set of modeling principles (e.g., “model-based OPC” employing predetermined behavior data to drive geometric manipulation of the data set) or a hybrid combination of rule-based OPC and model-based OPC.
Current methods provide corrected layouts in view of the overall lithography pattern. However, current methods are insufficient to effectively correct for all lithography weaknesses that may exist during translation of the integrated circuit device schematic into the physical representation or layout, especially in multiple patterning lithography processes that employ a plurality of individual masks and multiple exposures.
For example, certain current retargeting processes perform retargeting based on the overall combination or merger of decomposed layouts. An example of such a retargeting process is provided in FIG. 1. As shown, a circuit design layout 10 includes a pattern 12 of features 14. The pattern 12 is decomposed into a first decomposed layout 21 including first features 31, a second decomposed layout 22 including second features 32, and a third decomposed layout 23 including third features 33. In FIG. 1, the decomposed layouts are combined to form a combined layout 36. Then, based on the combined layout 36, a retargeting process is performed based on design rules for the combined layout 36. As a result, retargeted features 40 are defined in a retargeted combined layout 42.
Other retargeting processes may retarget each decomposed layout separately. However, such processes calculate the retargeting bias or adjustment based on the overall layout design rules. FIG. 2 illustrates such a retargeting process. In FIG. 2, process for decomposing the circuit design layout 10 is performed in accordance with the steps of FIG. 1 to form a first decomposed layout including first features 31, a second decomposed layout including second features 32, and a third decomposed layout including third features 33. In FIG. 2, the first features 31 are retargeted based on design rules for the overall layout pattern to form first retargeted features 41. Then, the second features 32 are retargeted based on design rules for the overall layout pattern 12 to form second retargeted features 42. Further, the third features 33 are retargeted based on design rules for the overall layout pattern 12 to form third retargeted features 43. While each set of features 31, 32 and 33 is retargeted separately, each is retargeted based on the overall layout pattern 12.
Accordingly, it is desirable to provide an improved method for retargeting a circuit design layout for a multiple patterning lithography process. In addition, it is desirable to provide method for fabricating a semiconductor device using such retargeted circuit design layouts. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.